Avago Technologies LSI53C1010R - Manual (Page 229)

SCSI Registers 4-111
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
40 4 4 100.00 5.00 2.50
40 8 0 200.00 2.50 2.50
40 8 1 200.00 2.50 2.00
40 8 2 200.00 2.50 1.67
40 8 3 200.00 2.50 1.43
40 8 4 200.00 2.50 1.25
1. Number Xclks = XCLKS_DT + XCLKS_ST + XCLKH_DT + XCLKH_ST.
Table 4.5 Single Transition Transfer Rates
Clock
(MHz) Divisor Number
Xclks
1
Base
Period
(ns)
Receive Rate
(Megatransfers/s)
Send Rate
(Megatransfers/s)
160 1 0 6.25 40.00 40.00
160 1 1 6.25 40.00 32.00
160 1 2 6.25 40.00 26.67
160 1.5 0 9.38 26.67 26.67
160 1.5 1 9.38 26.67 21.33
160 1.5 2 9.38 26.67 17.78
160 2 0 12.50 20.00 20.00
160 2 1 12.50 20.00 16.00
160 2 2 12.50 20.00 13.33
160 3 0 18.75 13.33 13.33
160 3 1 18.75 13.33 10.67
160 3 2 18.75 13.33 8.89
160 4 0 25.00 10.00 10.00
160 4 1 25.00 10.00 8.00
160 4 2 25.00 10.00 6.67
160 6 0 37.50 6.67 6.67
160 6 1 37.50 6.67 5.33
160 6 2 37.50 6.67 4.44
160 8 0 50.00 5.00 5.00
Table 4.4 Double Transition Transfer Rates (Cont.)
Clock
(MHz)
Divisor
Number
Xclks
1
Base
Period (ns)
Receive Rate
(Megatransfers/s)
Send Rate
(Megatransfers/s)