Avago Technologies LSI53C1010R - Manual (Page 67)

SCSI Functional Description 2-37
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
The LSI53C1010R supports 64-bit memory and automatically supports
misaligned DMA transfers. The FIFO allows the LSI53C1010R to support
4, 8, 16, 32, 64, or 128 Dword bursts across the PCI bus interface.
2.2.12 SCSI Data Paths
The data path through the LSI53C1010R is dependent on whether data
is moved into or out of the chip and whether the SCSI data transfer is
asynchronous or synchronous.
Figure 2.3 illustrates how data is moved
to and from the SCSI bus in each of the different modes. The following
sections determine whether any bytes remain in the data path when the
device halts an operation.
Figure 2.3 LSI53C1010R Host Interface SCSI Data Paths
2.2.12.1 Asynchronous SCSI Send
To determine the number of bytes remaining in the DMA FIFO when a
phase mismatch occurs, read the
DMA FIFO Byte Count (DFBC) register.
This 16-bit, read-only register contains the actual number of bytes
remaining in the DMA FIFO. In addition, the
SCSI Output Data Latch (SODL) register must be checked to determine
whether it contains any remaining bytes. If bit 5 (OLF) in the
SCSI Status Zero (SSTAT0) register is set, then the least significant byte
in the SODL register contains data. If bit 5 (OLF1) in the
PCI Interface
DMA FIFO
SODL Register
SCSI Interface
PCI Interface
DMA FIFO
SIDL Register
SCSI Interface
PCI Interface
DMA FIFO
SCSI Interface
PCI Interface
DMA FIFO
SCSI Interface
SCSI FIFO
Asynchronous
SCSI Send
Asynchronous
SCSI Receive
Synchronous
SCSI Send
Synchronous
SCSI Receive
SWIDE Register
Chain Byte
Holding Register
Chain Byte
Holding Register