Avago Technologies LSI53C1010R - Manual (Page 113)

Test Interface Signals 3-19
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
3.7 Test Interface Signals
Table 3.16 describes the Test Interface Signal group. Table 3.16 is
divided into Internal Test Signals and JTAG Signals.
Table 3.16 Test Interface Signals
Name Bump Type Strength Description
Internal Test Signals
SCAN_MODE E7 I N/A Scan Mode. For LSI Logic test purposes only. This
pin has a static pull-down.
SCANEN N22 I N/A SCANEN. For LSI Logic test purposes only. Pulled
LOW internally.
IDDTN Y4 I N/A IDDTN. For LSI Logic test purposes only. Pulled
LOW internally.
TEST_HSC D7 I N/A Test Halt SCSI Clock. For LSI Logic test purposes
only. Pulled LOW internally. This signal can also
cause a full chip reset.
TEST_RST/ AD5 I N/A Test Reset. For LSI Logic test purposes only.
Pulled HIGH internally.
JTAG Signals
TCK_CHIP AC6 I N/A Test Clock. This pin provides the clock for the
JTAG test logic. This pin has a static pull-up.
TMS_CHIP AE4 I N/A Test Mode Select (TMS). The signal received at
TMS is decoded by the Test Access Port (TAP)
controller to control JTAG test operations. This pin
has a static pull-up.
TDI_CHIP AF3 I N/A Test Data In. This pin receives the serial test
instructions for the JTAG test logic. This pin has a
static pull-up.
TDO_CHIP AD6 O 4 mA Test Data Out. This pin is the serial output for test
instructions and data from the JTAG test logic.