Avago Technologies LSI53C1010R - Manual (Page 198)

4-80 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
GPIO[4:2] GPIO Enable [4:2]
The general purpose control corresponds to bits [4:2] in
the
General Purpose (GPREG) register and to the
GPIO4–GPIO2 pins. GPIO4 powers-up as a
general purpose output. GPIO[3:2] power-up as
general purpose inputs.
GPIO[1:0] GPIO Enable [1:0]
These bits are set at power-up causing the GPIO1 and
GPIO0 pins to become inputs. Clearing these bits cause
GPIO[1:0] to become outputs.
Register: 0x48
SCSI Timer Zero (STIME0)
Read/Write
HTH[3:0] Handshake-to-Handshake Timer Period [7:4]
These bits select the handshake-to-handshake time-out
period, which is the maximum time between SCSI
handshakes (SREQ/ to SREQ/ in target mode; or,
SACK/ to SACK/ in the initiator mode). When this timing
is exceeded, an interrupt is generated and the HTH bit in
the
SCSI Interrupt Status One (SIST1) register is set.
The following table contains time-out periods for the
Handshake-to-Handshake Timer, the
Selection/Reselection Timer (bits [3:0]), and the
General Purpose Timer (
SCSI Timer One (STIME1) bits
[3:0]). For a more detailed explanation of interrupts, refer
to
Chapter 2, “Functional Description.”
7 4 3 0
HTH[3:0] SEL[3:0]
0 0 0 0 0 0 0 0