Scsi input data latch (sidl) – Avago Technologies LSI53C1010R User Manual
Page 208
4-90
Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
SCSI ID must both be asserted. Assert this bit in SCSI-2
systems so that a single bit error on the SCSI bus is not
interpreted as a single initiator response.
R
Reserved
3
TTM
Timer Test Mode
2
Setting this bit facilitates testing of the selection time-out,
general purpose, and handshake-to-handshake timers by
greatly reducing all three time-out periods. Setting this bit
starts all three timers. If the respective bits in the
SCSI Interrupt Enable One (SIEN1)
register are asserted,
the LSI53C1010R SCSI function generates interrupts at
time-out. This bit is intended for internal manufacturing
diagnosis and should not be used in normal operation.
CSF
Clear SCSI FIFO
1
Setting this bit causes the “full flags” for the SCSI FIFO to
be cleared. This empties the FIFO. This bit is self-clearing.
In addition to the SCSI FIFO pointers, the SIDL, SODL,
and SODR full bits in the
and
are cleared.
R
Reserved
0
Registers: 0x50–0x51
SCSI Input Data Latch (SIDL)
Read Only
SIDL
SCSI Input Data Latch
[15:0]
This register is used primarily for diagnostic testing,
programmed I/O operation, or error recovery.
Asynchronous Data received from the SCSI bus can be
read from this register. When receiving asynchronous
SCSI data, the data flows into this register and out to the
host FIFO. This register differs from the
register; the
contains latched data and
the
always contains exactly
what is currently on the SCSI data bus. Reading this
15
0
SIDL
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x