Memory move read selector (mmrs), Memory move write selector (mmws), Registers: 0xa0–0xa3 – Avago Technologies LSI53C1010R User Manual
Page 218: Registers: 0xa4–0xa7
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Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0xA0–0xA3
Memory Move Read Selector (MMRS)
Read/Write
MMRS
Memory Move Read Selector
[31:0]
This register supplies AD[63:32] for data read operations
during Memory-to-Memory Move and absolute address
LOAD operations.
A special mode of this register can be enabled by setting
the PCI Configuration Info Enable bit in the
register. If this bit is set, the
Memory Move Read Selector (MMRS)
register returns
bits [31:0] of the memory mapped operating register, PCI
Base Address Register Two (BAR2) (MEMORY)
, when
read. In this mode, writes to the MMRS register have no
effect. Clearing the PCI Configuration Info Enable bit
causes the MMRS register to return to normal operation.
Registers: 0xA4–0xA7
Memory Move Write Selector (MMWS)
Read/Write
MMWS
Memory Move Write Selector
[31:0]
This register supplies AD[63:32] for data write operations
during Memory-to-Memory Moves and absolute address
STORE operations.
A special mode of this register can be enabled by setting
the PCI Configuration Info Enable bit in the
register. If this bit is set, the
MMWS register returns bits [31:0] of the SCRIPT RAM PCI
Base Address Register Four (BAR4) (SCRIPTS RAM)
in
bits [31:0] of the MMWS register when read. In this mode,
31
0
MMRS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
0
MMWS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0