Avago Technologies LSI53C1010R - Manual (Page 327)

PCI and External Memory Interface Timing Diagrams 6-37
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
6.4.3 External Memory Timing
Tables 6.31 through 6.38 and figures 6.25 through 6.34 describe External
Memory timing.
Table 6.31 External Memory Read
Symbol Parameter
66 MHz PCI 33 MHz PCI
Unit Min Max Min Max
t
1
Shared signal input setup time 3 – 7 – ns
t
2
Shared signal input hold time 0 – 0 – ns
t
3
CLK to shared signal output valid 2 6 2 11 ns
t
11
Address setup to MAS/ HIGH 25 – 25 – ns
t
12
Address hold from MAS/ HIGH 15 – 15 – ns
t
13
MAS/ pulse width 25 – 25 – ns
t
14
MCE/ LOW to data clocked in 150 – 150 – ns
t
15
Address valid to data clocked in 205 – 205 – ns
t
16
MOE/ LOW to data clocked in 100 – 100 – ns
t
17
Data hold from address, MOE/, MCE/ change 0 – 0 – ns
t
19
Data setup to CLK HIGH 5 – 5 – ns