Avago Technologies LSI53C1010R User Manual
Page 68
2-38
Functional Description
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
register is set, then the most significant byte
in the SODL register contains data. Checking these bits also reveals bytes
left in the SODL register from a Chained Move operation with an odd byte
count. To recover from all other error conditions, clear the DMA FIFO by
setting bit 2 (CLF) in
and retry the I/O.
If the Wide SCSI Send (WSS) bit in the
register is set when a phase mismatch occurs, then adjustments must be
made to the previous block move, not the current block move loaded into
DCMD/DBC. To recover the byte of chain data in the SODL register, set
the previous block move byte count to 1 and set the address to the last
data address for that block move.
2.2.12.2 Synchronous SCSI Send
The DMA FIFO is the only location where data can reside when a phase
mismatch occurs during a synchronous SCSI send transfer. To determine
the number of bytes remaining in the DMA FIFO, read the
register. This 16-bit, read only register
contains the actual number of bytes remaining in the DMA FIFO. To
recover from all other error conditions, clear the DMA FIFO by setting bit
2 (CLF) in
and retry the I/O.
If the Wide SCSI Send (WSS) bit in the
register is set when a phase mismatch occurs, then adjustments must be
made to the previous block move, not the current block move loaded into
DCMD/DBC. To recover the byte of chain data in the outbound chain byte
holding register, set the previous block move byte count to one and set
the address to the last data address for that block move.
2.2.12.3 Asynchronous SCSI Receive
When a phase mismatch occurs during an asynchronous SCSI receive,
the only data that may remain in the device is a potential wide residue
byte in the
register. If bit 0 (WSR) in
is set, then the SWIDE register contains a
residual byte. This byte can be flushed by executing a block move
instruction with a byte count of one. To recover from all other error
conditions, set the DMA FIFO by setting bit 2 (CLF) in
and retry the I/O.