Avago Technologies LSI53C1010R - Manual (Page 384)

IX-8 Index
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
external
clock 6-11
memory
configuration 2-60
multiple byte accesses 6-13
read 6-37
timing 6-37
write 6-41
extra clock of data hold on DT transfer edge 4-103
extra clock of data hold on ST transfer edge 4-103
extra clock of data setup on DT transfer edge 4-104
extra clock of data setup on ST transfer edge 4-104
F
fast back to back capable 4-6
fatal interrupt 2-48
fetch enable (FE) 4-79
FIFO
byte control (FBL[2:0]) 4-57
byte control (FBL3) 4-57
clear SCSI 4-90
first dword 5-5 , 5-16 , 5-24 , 5-28 , 5-40
flash rom 3-18
flush DMA FIFO (FLF) 4-55
flushing (FLSH) 4-51
force bad AIP value 4-114
FRAME/ 3-7
full arbitration, selection/reselection 4-25
function complete (CMP) 4-70 , 4-74
G
general description 1-1
general purpose
I/O (GPIO[4:0]) 4-37
I/O pin 3-16 , 3-17
I/O pin 0 3-16
pin control (GPCNTL) 4-79
timer expired (GEN) 4-73 , 4-77
timer period (GEN[3:0]) 4-83
timer scale factor (GENSF) 4-82
general purpose register 4-36
GNT/ 2-11 , 3-8
GPIO enable 4-80
grant 2-11 , 3-8
H
halting 2-51
handshake-to-handshake
timer bus activity enable (HTHBA) 4-82
timer expired (HTH) 4-73 , 4-77
timer period (HTH[7:4]) 4-80
timer scale factor (HTHSF) 4-83
hardware control of SCSI activity LED 2-21
hardware interrupts 2-46
header type (HT[7:0]) 4-8
high impedance mode 4-88
high voltage differential mode
description 2-39
HVD 2-39
I
I/O 3-2
instructions 5-16
read command 2-6
space 2-3 , 2-4
write command 2-6
IDDTN 3-19
IDSEL 2-3 , 3-8
illegal instruction detected (IID) 4-42 , 4-66
immediate
arbitration (IARB) 4-29
data 5-25
index mode 0 5-9
index mode 1 5-9
indirect addressing 5-5
initialization device select 3-8
initiator
asynchronous receive 6-59
asynchronous send 6-58
mode 5-12 , 5-18
phase mismatch 4-74
ready 3-7
synchronous transfer 6-62 , 6-65
timing 6-21
input 3-2
capacitance 6-4
current as a function of input voltage 6-9
signals 6-6
instruction
address (IA) 4-119
type 5-40
block move 5-5
I/O instruction 5-16
memory move 5-37
read/write instruction 5-24
transfer control instruction 5-29
INTA routing enable 3-22
INTA/ 2-46 , 2-52 , 3-9 , 3-22 , 4-66
INTB/ 2-46 , 2-52 , 3-9 , 3-22 , 4-66
INTC/ 2-53
INTD/ 2-53
interface
128, 256, 512 Kbyte or 1 Mbyte
150 ns memory B-11