Scsi test three (stest3), Register: 0x4f – Avago Technologies LSI53C1010R User Manual
Page 207
SCSI Registers
4-89
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Note:
It is not necessary to set this bit for access to the SCSI
bit-level registers (
,
, and input registers).
Register: 0x4F
SCSI Test Three (STEST3)
Read/Write
TE
TolerANT Enable
7
Setting this bit enables the active negation portion of
TolerANT technology. Active negation causes the SCSI
Request, Acknowledge, Data, and Parity signals to be
actively deasserted, instead of relying on external
pull-ups, when the LSI53C1010R SCSI function is driving
these signals. Active deassertion of these signals occurs
only when the LSI53C1010R SCSI function is in an
information transfer phase. When performing synchronous
transfers, TolerANT technology should be enabled to
improve setup and deassertion times. Active negation is
disabled after reset or when this bit is cleared. For details
on TolerANT technology, refer to
R
Reserved
6
HSC
Halt SCSI Clock
5
Setting this bit causes the internal divided SCSI clock to
come to a stop in a glitchless manner. This bit is used for
test purposes or to lower I
DD
during a power-down mode.
Refer to
Chapter 2, “Functional Description,”
for operation
of the SCSI clock quadrupler.
DSI
Disable Single Initiator Response
4
If this bit is set, the LSI53C1010R SCSI function ignores
all bus-initiated selection attempts that employ the
single-initiator option from SCSI-1. In order to select the
LSI53C1010R SCSI function while this bit is set, the
LSI53C1010R SCSI function’s SCSI ID and the initiator’s
7
6
5
4
3
2
1
0
TE
R
HSC
DSI
R
TTM
CSF
R
0
0
0
0
0
0
0
0