Base address register zero (bar0) (i/o), Base address register one (bar1) (memory), Reserved – Avago Technologies LSI53C1010R User Manual
Page 127: Register: 0x0f
PCI Configuration Registers
4-9
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x0F
Reserved
This register is reserved.
Registers: 0x10–0x13
Base Address Register Zero (BAR0) (I/O)
Read/Write
BAR0
Base Address Register Zero – I/O
[31:0]
This base address register maps the operating register
set into I/O space. The LSI53C1010R requires 256 bytes
of I/O space for this base address register. Bit 0 is hard-
wired to one. Bit 1 is reserved and returns a zero on all
reads. All other bits map the device into I/O space. For
detailed information on the operation of this register, refer
to the PCI 2.2 specification.
Registers: 0x14–0x17
Base Address Register One (BAR1) (MEMORY)
Read/Write
BAR1
Base Address Register One
[31:0]
This base address register, in conjunction with
Base Address Register Two (BAR2) (MEMORY)
, maps
SCSI operating registers into memory space and
represents the lower 32 bits of the memory address. Bits
[9:0] are hardwired to 0b0000000100. The default value
of this register is 0x00000004. The LSI53C1010R
7
0
R
0
0
0
0
0
0
0
0
31
0
BAR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
31
0
BAR1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0