Avago Technologies LSI53C1010R - Manual (Page 41)

PCI Functional Description 2-11
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.1.3 Internal Arbiter
The PCI to SCSI controller uses a single REQ/ - GNT/ signal pair to
arbitrate for access to the PCI bus. An internal arbiter circuit allows the
different bus mastering functions resident in the chip to arbitrate among
themselves for the privilege of arbitrating for PCI bus access. There are
two independent bus mastering functions inside the LSI53C1010R, one
for each of the SCSI functions.
The internal arbiter uses a round robin arbitration scheme to decide
which internal bus mastering function may arbitrate for access to the PCI
bus. This ensures that no function is starved for access to the PCI bus.
2.1.4 PCI Cache Mode
The LSI53C1010R supports the PCI specification for an 8-bit
Cache Line Size (CLS) register located in the PCI configuration space. The
Cache Line Size (CLS) register provides the ability to sense and react to
nonaligned addresses corresponding to cache line boundaries. In
conjunction with the
Cache Line Size (CLS) register, the PCI commands
Memory Read Line (MRL), Memory Read Multiple (MRM), and
Memory Write and Invalidate (MWI) are individually software enabled or
disabled.
Table 2.2 provides information on the PCI cache mode alignment.