Scsi control three (scntl3), Register: 0x03 – Avago Technologies LSI53C1010R User Manual
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Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x03
SCSI Control Three (SCNTL3)
Read/Write
This register is automatically loaded when a Table Indirect Select or
Reselect SCRIPTS instruction is executed.
R
Reserved
7
SCF[2:0]
Synchronous Clock Conversion Factor
[6:4]
These bits select a factor by which the frequency of
SCLK is divided before being presented to the
synchronous SCSI control logic. The synchronous
transfer speed is determined by the combination of the
divided clock and the setting of the XCLKS and XCLKH
bits in the
register. The
following table shows the clock dividers that are available.
Refer to the table in the
register description for a full list of available transfer rates.
EWS
Enable Wide SCSI
3
When this bit is cleared, all information transfer phases
are assumed to be eight bits, transmitted on SD[7:0]/ and
SDP0/. When this bit is asserted, data transfers are
performed 16 bits at a time; the least significant byte is
on SD[7:0]/ and SDP0/, and the most significant byte is
7
6
4
3
2
0
R
SCF[2:0]
EWS
R
0
0
0
0
0
0
0
0
SCF2
SCF1
SCF0
Factor
Frequency
0
0
0
SCLK/3
0
0
1
SCLK/1
0
1
0
SCLK/1.5
0
1
1
SCLK/2
1
0
0
SCLK/3
1
0
1
SCLK/4
1
1
0
SCLK/6
1
1
1
SCLK/8