Avago Technologies LSI53C1010R - Manual (Page 93)

Power Management 2-63
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.5.3 Power State D2
Power state D2 is a lower power state than D1. A function in this state
places the LSI53C1010R core in the coma mode. The following PCI
Configuration Space
Command register enable bits are suppressed:
•
I/O Space Enable
•
Memory Space Enable
•
Bus Mastering Enable
•
SERR/Enable
•
Enable Parity Error Response
Thus, the function's memory and I/O spaces cannot be accessed, and the
function cannot be a PCI bus master. Furthermore, SCSI and DMA
interrupts are disabled when the function is in power state D2. If the
function is changed from power state D2 to power state D1 or D0, the
previous values of the PCI
Command register are restored. Also, any
pending interrupts before the function entered power state D2 are asserted.
2.5.4 Power State D3
Power state D3, the minimum power state, includes settings called D3hot
and D3cold. D3hot allows the device to transition to D0 using software.
The LSI53C1010R is considered to be in power state D3cold when
power is removed from the device. D3cold can transition to D0 by
applying V
CC
and resetting the device.
Power state D3 is a lower power level than power state D2. A function in
this state places the LSI53C1010R core in the coma mode. Furthermore,
the function's soft reset is continually asserted while in power state D3,
which clears all pending interrupts and 3-states the SCSI bus. In
addition, the function's PCI
Command register is cleared. If both of the
LSI53C1010R functions are placed in power state D3, the Clock
Quadrupler is disabled, which results in additional power savings.