Avago Technologies LSI53C1010R - Manual (Page 204)

4-86 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
SCSI operations. When this bit is set, and if the
LSI53C1010R is functioning as an initiator, the device is
waiting for the target to request data transfers. When this
bit is set, and if the LSI53C1010R is functioning as a
target, then the initiator has sent the offset number of
acknowledges.
SOM SCSI Synchronous Offset Maximum 0
This bit indicates that the current synchronous SREQ/,
SACK/ offset is the maximum specified by bits [5:0] in the
SCSI Transfer (SXFER) register. This bit is not latched
and may change at any time. It is used in low level
synchronous SCSI operations. If this bit is set and if the
LSI53C1010R is functioning as a target, it is waiting for
the initiator to acknowledge the data transfers. If the
LSI53C1010R SCSI is functioning as an initiator, the
target has sent the offset number of requests.
Register: 0x4D
SCSI Test One (STEST1)
Read/Write
R Reserved [7:6]
DOSGE Disable Outbound SCSI Gross Errors 5
When set, this bit disables all SCSI gross errors related
to outbound data transfers.
DISGE Disable Inbound SCSI Gross Errors 4
When set, this bit disables all SCSI gross errors related
to inbound data transfers.
QEN SCLK Quadrupler Enable 3
This bit, when set, powers up the internal clock
quadrupler circuit, which quadruples the SCLK 40 MHz
clock to the internal 160 MHz SCSI clock required for
Ultra2 and Ultra160 SCSI operation. When cleared, this
bit powers down the internal quadrupler circuit. Refer to
Chapter 2, “Functional Description,” for information
concerning the operation of the quadrupler.
7 6 5 4 3 2 1 0
R DOSGE DISGE QEN QSEL IRM[1:0]
0 0 0 0 0 0 0 0