Avago Technologies LSI53C1010R - Manual (Page 192)

4-74 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x42
SCSI Interrupt Status Zero (SIST0)
Read Only
Reading the SCSI Interrupt Status Zero (SIST0) register returns the
status of the various interrupt conditions, whether they are enabled in the
SCSI Interrupt Enable Zero (SIEN0) register or not. Each bit set indicates
occurrence of the corresponding condition. Reading the SIST0 clears the
interrupt status.
Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register because additional
interrupts may be pending; the LSI53C1010R SCSI functions stack
interrupts. SCSI interrupt conditions are individually masked through the
SCSI Interrupt Enable Zero (SIEN0) register.
When performing consecutive 8-bit reads of the DMA Status (DSTAT) ,
SCSI Interrupt Status Zero (SIST0) , and SCSI Interrupt Status One (SIST1)
registers (in any order), insert a delay equivalent to 12 clock periods
between the reads to ensure the interrupts clear properly. Also, if reading
the registers when both the
Interrupt Status Zero (ISTAT0) SIP and DIP bits
may not be set, read the SIST0 and SIST1 registers before the DSTAT
register to avoid missing a SCSI interrupt. For details on interrupts refer to
Chapter 2, “Functional Description.”
M/A Initiator Mode: Phase Mismatch; Target Mode:
SATN/ Active
7
In the initiator mode, this bit is set if the SCSI phase
asserted by the target does not match the instruction.
The phase is sampled when SREQ/ is asserted by the
target. In the target mode, this bit is set when the SATN/
signal is asserted by the initiator.
CMP Function Complete 6
This bit is set when an arbitration only or full arbitration
sequence is completed.
7 6 5 4 3 2 1 0
M/A CMP SEL RSL SGE UDC RST PAR
0 0 0 0 0 0 0 0