Avago Technologies LSI53C1010R - Manual (Page 48)

2-18 Functional Description
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Write Example 3 – Burst = 16 Dwords; Cache Line Size = 8 Dwords:
2.1.4.6 Memory-to-Memory Moves
Memory-to-Memory Moves also support PCI cache commands, as
described, with one limitation: Memory Write and Invalidate on
Memory-to-Memory Move writes are only supported if the source and
destination address are quad word aligned. If the source and destination
are not quad word aligned, that is,
Source Address[2:0] == Destination Address[2:0], write alignment is not
performed and Memory Write and Invalidates are not issued.
The LSI53C1010R is little endian. This mode assigns the least significant
byte to bits [7:0].
2.2 SCSI Functional Description
Both Ultra160 SCSI controllers on the LSI53C1010R support either an
8-bit or 16-bit SCSI bus. Each controller supports Wide Ultra160 SCSI
synchronous transfer rates up to 160 Mbytes/s on an LVD SCSI bus.
SCSI functions can be programmed with SCSI SCRIPTS, making it easy
to “fine tune” the system for specific mass storage devices or Ultra160
SCSI requirements.
Figure 2.1 on page 2-2 illustrates the relationship
between the LSI53C1010R modules.
A to B: MW (6 bytes)
A to C: MW (13 bytes)
A to D: MW (17 bytes)
C to D: MW (5 bytes)
C to E: MW (21 bytes)
D to F: MW (32 bytes)
A to H: MW (31 bytes)
MWI (32 bytes)
MW (18 bytes)
A to G: MW (31 bytes)
MWI (32 bytes)
MW (3 bytes)