Avago Technologies LSI53C1010R - Manual (Page 388)

IX-12 Index
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
rise and fall time test condition 6-8
ROM 2-59
expansion enable 4-14
flash and memory interface signals 3-18
slow ROM pin 3-23
routing interrupts 2-53
routing, RAID ready 2-53
RST/ 3-5
S
SACK 2-51
SACs 2-21
scan mode 3-19
SCAN_MODE 3-4 , 3-19
SCANEN 3-19
SCF divisor values 2-42
SCLK 3-10
quadrupler enable (QEN) 4-86
quadrupler select (QSEL) 4-87
scratch
byte register (SBR) 4-67
register A (SCRATCHA) 4-63 , 4-125
register B (SCRATCHB) 4-99 , 4-128
registers C–R (SCRATCHC–SCRATCHR) 4-99
script fetch selector (SFS) 4-101 , 4-129
SCRIPTS 2-57
64-bit addressing 2-21
block move
index mode 0 5-9
index mode 1 5-9
indirect addressing 5-5
instruction type 5-5
opcode 5-10
SCSI phase 5-13
start address 5-15
table indirect addressing 5-7
transfer counter 5-14
block move instructions 5-5
call instruction 5-30
chained block moves 2-55
clear instruction 5-18
disable internal RAM cycles 4-94
disconnect instruction 5-17
DMA pointer 4-62
DMA pointer save 4-62
I/O
encoded SCSI destination ID 5-22
instruction type 5-16
opcode 5-16
relative addressing mode 5-20
select with ATN/ 5-22
set/clear carry 5-22
set/clear SACK/ 5-23
set/clear SATN/ 5-23
set/clear target mode 5-22
start address 5-24
table indirect mode 5-20
I/O instructions 5-16
instruction prefetch 2-31
internal RAM 2-20
interrupt instruction 5-31
interrupt instruction received (SIR) 4-42 , 4-66
interrupt-on-the-fly instruction 5-31
jump instruction 5-29
load and store
byte count 5-41
DSA relative 5-40
instruction type 5-40
instructions 2-33
load/store 5-41
memory I/O address and DSA offset 5-42
no flush 5-41
register address 5-41
memory move
DSPS register 5-38
instruction type 5-37
no flush 5-37
TEMP register 5-39
transfer count 5-37
operation 5-1
overview 5-4
phase mismatch handling 2-19
processor 2-19
internal RAM for instruction storage 2-20
performance 2-19
RAM 2-4 , 2-20
read/write
A[6:0] 5-25
destination address 5-26
immediate data 5-25
instruction type 5-24
opcode 5-25
operator 5-25
upper register address line [A7] 5-25
use data8/SFBR 5-25
reselect instruction 5-16
return instruction 5-30
running (SRUN) 4-51
select instruction 5-18
set instruction 5-17 , 5-19
transfer control
32/64-bit jump 5-33
carry test 5-33
compare data 5-34
compare phase 5-34