Avago Technologies LSI53C1010R - Manual (Page 319)

PCI and External Memory Interface Timing Diagrams 6-29
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Table 6.27 Burst Read, 32-Bit Address and Data
Symbol Parameter
66 MHz PCI 33 MHz PCI
Unit Min Max Min Max
t
1
Shared signal input setup time 3 – 7 – ns
t
2
Shared signal input hold time 0 – 0 – ns
t
3
CLK to shared signal output valid 2 6 2 11 ns