Avago Technologies LSI53C1010R - Manual (Page 352)

6-62 Specifications
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.39 Initiator and Target ST Synchronous Transfer
Table 6.46 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or 80.0 Mbyte
(16-Bit Transfers) Quadrupled 40 MHz Clock
Symbol Parameter Min Max Unit
t
ST1
Send SREQ/ or SACK/ assertion pulse width 8 – ns
t
ST2
Send SREQ/ or SACK/ deassertion pulse width 8 – ns
t
ST1
Receive SREQ/ or SACK/ assertion pulse width 6.5 – ns
t
ST2
Receive SREQ/ or SACK/ deassertion pulse width 6.5 – ns
t
ST3
Send data setup to SREQ/ or SACK/ asserted 9.5 – ns
t
ST4
Send data hold from SREQ/ or SACK/ asserted 9.5 – ns
t
ST5
Receive data setup to SREQ/ or SACK/ asserted 4.5 – ns
t
ST6
Receive data hold from SREQ/ or SACK/ asserted 4.5 – ns
t
ST1
SREQ/SACK
Send Data
(SD[15:0]/)
Receive Data
(SD[15:0]/)
t
ST2
t
ST3
t
ST4
t
ST6
t
ST5