Avago Technologies LSI53C1010R - Manual (Page 265)

I/O Instructions 5-17
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
If the LSI53C1010R wins arbitration, it attempts to
reselect the SCSI device whose ID is defined in the
destination ID field of the instruction. When the
LSI53C1010R wins arbitration, it fetches the next
instruction from the address pointed to by the
DMA SCRIPTS Pointer (DSP) register. This way the
SCRIPTS can move on to the next instruction before the
reselection completes. It continues executing SCRIPTS
until a SCRIPT that requires a response from the initiator
is encountered.
If the LSI53C1010R is selected or reselected before
winning arbitration, it fetches the next instruction from the
address pointed to by the 32-bit jump address field stored
in the
DMA Next Address (DNAD) register. Manually set
the LSI53C1010R to the initiator mode if it is reselected,
or to the target mode if it is selected.
Disconnect Instruction
The LSI53C1010R disconnects from the SCSI bus by
deasserting all SCSI signal outputs.
Wait Select Instruction
If the LSI53C1010R is selected, it fetches the next
instruction from the address pointed to by the
DMA SCRIPTS Pointer (DSP) register.
If reselected, the LSI53C1010R fetches the next
instruction from the address pointed to by the 32-bit jump
address field stored in the
DMA Next Address (DNAD)
register. Manually set the LSI53C1010R to the initiator
mode when it is reselected.
If the CPU sets the SIGP bit in the
Interrupt Status Zero (ISTAT0) register, the LSI53C1010R
aborts the Wait Select instruction and fetches the next
instruction from the address pointed to by the 32-bit jump
address field stored in the
DMA Next Address (DNAD)
register.
Set Instruction
When the SACK/ or SATN/ bits are set, the corresponding
bits in the
SCSI Output Control Latch (SOCL) register are
set. Do not set SACK/ or SATN/ except for testing
purposes. When the target bit is set, the corresponding