Avago Technologies LSI53C1010R - Manual (Page 39)

PCI Functional Description 2-9
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Read Multiple with Read Line Enabled – When both the Read
Multiple and Read Line modes are enabled, the Read Line command is
not issued if these conditions are met. Instead, a Read Multiple
command is issued.
If the Read Multiple mode is enabled, Read Multiple commands are
issued if the Read Multiple conditions are met.
2.1.2.13 Memory Write and Invalidate Command
The Memory Write and Invalidate command is identical to the
Memory Write command, except it additionally guarantees a minimum
transfer of one complete cache line. That is, the master intends to write
all bytes within the addressed cache line in a single PCI transaction
unless interrupted by the target. This command requires implementation
of the PCI
Cache Line Size (CLS) register. The LSI53C1010R enables
Memory Write and Invalidate cycles when bit 0 (WRIE), in the
Chip Test Three (CTEST3) register, and bit 4 (WIE), in the PCI
Command register, are set.
When the following conditions are met, Memory Write and Invalidate
commands are issued:
•
The following bits are set:
– The CLSE bit (Cache Line Size Enable, bit 7, of the
DMA Control (DCNTL) register),
– The WRIE bit (Write and Invalidate Enable, bit 0, of the
Chip Test Three (CTEST3) register),
– Bit 4 of the PCI Configuration Command register.
•
The Cache Line Size (CLS) register for each function contains a
legal burst size value (8, 16, 32, 64, or 128 Dwords) that is less than
or equal to the
DMA Mode (DMODE) burst size.
•
The chip has enough bytes in the DMA FIFO to complete at least
one full cache line burst.
•
The chip is aligned to a cache line boundary.
When these conditions are met, the LSI53C1010R issues a Write and
Invalidate command instead of a Memory Write command during all PCI
write cycles.