Avago Technologies LSI53C1010R - Manual (Page 58)

2-28 Functional Description
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
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The SCSI Status Two (SSTAT2) register:
– Bit 2 is reserved. HVD SCSI is not supported.
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The SCSI Interrupt Enable Zero (SIEN0) register:
– Bit 0, PAR (SCSI Parity/CRC/AIP Error), is set to detect a
parity/CRC/AIP error while receiving or sending SCSI data. For
more information, refer to
SCSI Control One (SCNTL1) , bit 5.
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The Chip Control Three (CCNTL3) register:
– Bit 4, ENDSKEW (Enable REQ/ACK to Data skew control) is set
to enable control of the relative skew between the SCSI
REQ/ACK signal and the data signals.
– Bits [3:2], DSKEW[1:0] (REQ/ACK – Data skew control), control
the amount of skew between the SCSI REQ/ACK signal and the
SCSI data signals. These bits are used for Ultra160 SCSI
domain validation only and control the skew only if bit 4 is set.
– Bits [1:0], LVDDL[1:0] (LVD Drive strength select), control the
drive level of the LVD pad drivers. This feature is intended for use
in Ultra160 SCSI domain validation testing environments only.
Set these bits to 0b00 during normal operation.
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The SCSI Control Four (SCNTL4) register:
– Bit 7, U3EN (Ultra160 Transfer Enable) is set to enable Ultra160
transfers.
– Bit 6, AIPCKEN (AIP Checking Enable), is set to enable checking
of the upper byte lane of protection information during
Command, Status, and Message Phases.
– Bits [5:4] are reserved.
– Bit 3, XCLKH_DT (Extra Clock of Data Hold on DT Transfer Edge)
is set to add a clock of data hold to synchronous DT SCSI
transfers on the DT edge.
– Bit 2, XCLKH_ST (Extra Clock of Data Hold on ST Transfer Edge)
is set to add a clock of data hold to synchronous DT or ST SCSI
transfers on the ST edge. This bit impacts both ST and DT
transfers because it affects data hold to the ST edge.