Avago Technologies LSI53C1010R - Manual (Page 190)

4-72 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
register. It can be accessed by setting bit 7, the Enable
Shadowed SGE Register (ShSGE) bit, in the
Chip Control Two (CCNTL2) register.
UDC Unexpected Disconnect 2
This condition only occurs in the initiator mode. It
happens when the target, which the LSI53C1010R SCSI
function is connected to, unexpectedly disconnects from
the SCSI bus. Refer to the SCSI Disconnect Unexpected
bit in the
SCSI Control Two (SCNTL2) register for details
about expected versus unexpected disconnects. Any
disconnect in the low level mode causes this condition.
RST SCSI Reset Condition 1
Indicates assertion of the SRST/ signal by the
LSI53C1010R SCSI function or any other SCSI device.
This condition is edge-triggered, so multiple interrupts
cannot occur because of a single SRST/ pulse.
PAR SCSI Parity/CRC/AIP Error 0
This bit indicates the LSI53C1010R SCSI function
detected a Parity/CRC/AIP error while receiving or sending
SCSI data. Refer to the Disable Halt on Parity/CRC/AIP
error or SATN/ Condition bits in the SCNTL1 register for
details about when this condition is raised.
Register: 0x41
SCSI Interrupt Enable One (SIEN1)
Read/Write
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the
SCSI Interrupt Status One (SIST1)
register. An interrupt is masked by clearing the appropriate mask bit. For
details on interrupts refer to
Chapter 2, “Functional Description.”
R Reserved [7:5]
7 5 4 3 2 1 0
R SBMC R STO GEN HTH
x x x 0 x 0 0 0