Avago Technologies LSI53C1010R - Manual (Page 111)

General Purpose I/O (GPIO) Signals 3-17
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Table 3.14 SCSI Function B GPIO Signals
Name Bump Type Strength Description
B_GPIO0 M25 I/O 8 mA SCSI Function B General Purpose I/O pin 0. This pin
is programmable at power-up through the MAD7 pin to
serve as the data signal for the serial EEPROM interface.
When GPIO0 is not in the process of downloading
EEPROM data, it can drive a SCSI Activity LED if bit 5
in the
General Purpose Pin Control (GPCNTL) register is
set. Or, it can indicate that the next bus request is an
opcode fetch if bit 6 in the GPCNTL register is set.
B_GPIO1 L25 I/O 8 mA SCSI Function B General Purpose I/O pin 1. This pin
is programmable at power-up through the MAD7 pin to
serve as the clock signal for the serial EEPROM
interface. If bit 7 of the
General Purpose Pin Control (GPCNTL) register is set,
this pin is driven LOW when the LSI53C1010R is the
bus master.
B_GPIO2 L23 I/O 8 mA SCSI Function B General Purpose I/O pin 2. This pin
powers up as an input.
B_GPIO3 K25 I/O 8 mA SCSI Function B General Purpose I/O pin 3. This pin
powers up as an input.
B_GPIO4 K23 I/O 8 mA SCSI Function B General Purpose I/O pin 4. This pin
powers up as an output. It can be used as the enable
line for V
PP
, the 12 V power supply to the external flash
memory interface.