Avago Technologies LSI53C1010R - Manual (Page 52)

2-22 Functional Description
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
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Bit 5 (LED_CNTL) in the General Purpose Pin Control (GPCNTL)
register is set,
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Bit 6 (Fetch Enable) in the General Purpose Pin Control (GPCNTL)
register is cleared,
•
The LSI53C1010R is not performing an EEPROM autodownload.
The CON (Connected) bit in Interrupt Status Zero (ISTAT0) is set anytime
the LSI53C1010R is connected to the SCSI bus either as an initiator or
a target. This happens after the LSI53C1010R has successfully
completed a selection or when it has successfully responded to a
selection or reselection. The CON bit is also set when the LSI53C1010R
wins arbitration in low level mode.
2.2.5 Designing an Ultra160 SCSI System
Software modifications are needed to take advantage of the Ultra160
speed in the LSI53C1010R. Because Ultra160 SCSI is based on existing
SCSI standards, it can use existing drivers if they are able to negotiate
for Ultra160 synchronous transfer rates. Also, the target device must be
able to communicate at Ultra160 speed. The LSI53C1010R uses domain
validation to determine whether or not the system is capable of Ultra160
SCSI before activating DT clocking. Refer to
Section 2.2.5.1, “Ultra160 Features,” for more information on DT clocking.
LVD SCSI fulfills the hardware requirements for Ultra160 SCSI transfer
rates, increased cable lengths, and additional devices on the bus. All
devices on the bus must have LVD SCSI capabilities to guarantee
Ultra160 SCSI transfer rates. For details on Ultra160 SCSI, refer to the
SCSI Parallel Interface-3 (SPI-3) working document that is available on
the world wide web at the T10 Home Page,
http://www.t10.org . Also,
check the SCSI Trade Association web site at
http://www.scsita.org/ . Chapter 6, “Specifications,” contains Ultra160
SCSI timing information. In addition to the guidelines in the draft
standard, make the following software adjustments to accommodate
Ultra160 SCSI transfers.