Avago Technologies LSI53C1010R - Manual (Page 216)

4-98 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x5B
Chip Control Three (CCNTL3)
Read/Write
R Reserved [7:5]
ENDSKEW Enable REQ/ACK to Data Skew Control 4
Setting this bit enables the control of the relative skew
between the SCSI REQ/ACK signals and the data
signals. The actual amount of skew time is controlled by
DSKEW[1:0] in this register.
DSKEW[1:0] Setup Data Skew Control [3:2]
These bits control the amount of skew between the SCSI
REQ/ACK signal and the SCSI data signals during setup.
The skew is affected only if the ENDSKEW bit is set.
Note: These bits are used for Ultra160 SCSI domain validation only
and should not be set during normal data transfer operations.
LVDDL[1:0] LVD Drive Strength Select [1:0]
These bits control the drive level of the LVD pad drivers.
Note: This feature is for Ultra160 SCSI domain validation testing
environments only and should not be set during normal
data transfer operations.
The following table shows the relative strength increase
or decrease based on the LVDDL values.
Note: If one of the LVDDL [1:0] bits are set on either channel,
both channels are affected.
7 5 4 3 2 1 0
R ENDSKEW DSKEW[1:0] LVDDL[1:0]
0 0 0 0 0 0 0 0
LVDDL Drive Level
00 Nominal
01
−
20% Nominal
10 +20% Nominal
11 Reserved