Avago Technologies LSI53C1010R - Manual (Page 307)

PCI and External Memory Interface Timing Diagrams 6-17
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.13 Operating Registers/SCRIPTS RAM Read, 32 Bits
Table 6.19 Operating Register/SCRIPTS RAM Read, 32 Bits
Symbol Parameter
66 MHz PCI 33 MHz PCI
Unit Min Max Min Max
t
1
Shared signal input setup time 3 – 7 – ns
t
2
Shared signal input hold time 0 – 0 – ns
t
3
CLK to shared signal output valid 2 6 2 11 ns
Data
Byte Enable
Addr In
CMD
t
2
t
1
t
2
t
1
t
2
t
1
t
1
t
2
t
2
t
3
t
2
t
1
t
3
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD[31:0]
(Driven by Master-Addr;
C_BE[3:0]/
(Driven by Master)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1010R)
STOP/
(Driven by LSI53C1010R)
DEVSEL/
(Driven by LSI53C1010R)
Out
t
3
In Out
t
3
LSI53C1010R Data)
LSI53C1010R Data)