Avago Technologies LSI53C1010R - Manual (Page 298)

6-8 Specifications
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.3 Rise and Fall Time Test Condition
Figure 6.4 SCSI Input Filtering
C
P
Capacitance per pin – 8 pF PQFP
t
R
2
Rise time, 10% to 90% 6.7 14.7 ns Figure 6.3
t
F
Fall time, 90% to 10% 5.7 17.2 ns Figure 6.3
dV
H
/dt Slew rate LOW to HIGH 100 470 mV/ns Figure 6.3
dV
L
/dt Slew rate HIGH to LOW 110 440 mV/ns Figure 6.3
ESD Electrostatic discharge 2 – KV MIL-STD-883C;
3015-7
Latch-up 100 – mA –
Filter delay 20 30 ns Figure 6.4
Ultra filter delay 10 15 ns Figure 6.4
Ultra2 filter delay 5 8 ns Figure 6.4
Extended filter delay 40 60 ns Figure 6.4
1. These values are guaranteed by periodic characterization; they are not 100% tested on every device.
2. Active negation outputs only: Data, Parity, SREQ/, SACK/. SCSI mode only (minus pins).
3. Single pin only; irreversible damage may occur if sustained for one second.
Table 6.13 TolerANT Technology Electrical Characteristics for SE SCSI Signals
1
(Cont.)
Symbol Parameter Min Max Unit Test Conditions
+
−
2.5 V
47
Ω
20 pF
REQ/ or ACK/ Input
t
1
V
TH
Note: t
1
is the input filtering period.