Avago Technologies LSI53C1010R - Manual (Page 51)

SCSI Functional Description 2-21
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
target wait states drop from 5 to 3. SCRIPTS RAM must first be written
before being read in order to initialize SCRIPTS RAM parity. If a SCRIPTS
RAM parity error is encountered, a SCSI Gross Error interrupt is signaled.
A complete set of development tools is available for writing custom
drivers with SCSI SCRIPTS. For more information on the SCSI SCRIPTS
instructions supported by the LSI53C1010R, refer to
Chapter 5, “SCSI SCRIPTS Instruction Set.”
2.2.3 64-Bit Addressing in SCRIPTS
The PCI interface for the LSI53C1010R provides 64-bit address and data
capability in the initiator mode. The chip can also respond to 64-bit
addressing in the target mode.
DACs can be generated for all SCRIPTS operations. There are six selector
registers that hold the upper Dword of a 64-bit address. All but one of these
is static and requires manual loading using a CPU access, a Load and
Store instruction, or a memory move instruction. One of the selector
registers is dynamic and is used during 64-bit direct block moves only. All
selectors default to zero, meaning the LSI53C1010R powers-up in a state
where only Single Address Cycles (SACs) are generated. When any of the
selector registers are written to a nonzero value, DACs are generated.
Direct, Table Indirect and Indirect Block Moves, Memory-to-Memory
Moves, Load/Stores, and Jumps are all instructions with 64-bit address
capability.
Note: Crossing the 4 Gbyte boundary on any one SCRIPTS
operation is not permitted. Therefore, software must handle
all such transactions.
2.2.4 Hardware Control of SCSI Activity LED
The LSI53C1010R controls an LED through the GPIO_0 pin to indicate
that it is connected to the SCSI bus. This function was previously
handled by a software driver.
Bit 3 (CON), in the Interrupt Status Zero (ISTAT0) register, is presented
at the GPIO_0 pin when the following occurs: