beautypg.com

4 serial eeprom interface, 1 default download mode, Serial eeprom interface – Avago Technologies LSI53C1010R User Manual

Page 90: Default download mode, Section 2.4, “serial eeprom interface

background image

2-60

Functional Description

Version 2.2

Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.

To use one of these configurations in a host adapter board design, put
4.7 k

pull-up resistors on the MAD pins corresponding to the available

memory space. Each MAD pin has an internal static pull-down; therefore,
no external pull-down resistors are needed. For example, to connect to
a 64 Kbyte external ROM, use a pull-up on MAD[2]. If the external
memory interface is not used, MAD[3:1] should be pulled HIGH.

The LSI53C1010R allows the system to determine the size of the
available external memory using the Expansion ROM Base Address
register in the PCI configuration space. For more information on how this
works, refer to the PCI specification or the Expansion ROM Base
Address register description in

Chapter 4, “Registers.”

MAD[0] is the slow ROM pin. When pulled up, it enables two extra clock
cycles of data access time to allow use of slower memory devices. The
external memory interface also supports updates to flash memory.

2.4 Serial EEPROM Interface

For each SCSI function, the LSI53C1010R implements an interface
permitting attachment of a serial EEPROM device to the GPIO[0] and
GPIO[1] pins. There are two modes of operation relating to the serial
EEPROM, the Subsystem ID register, and the Subsystem Vendor ID
register for each SCSI function. These modes are programmable through
the MAD[7] pin, which is sampled at power-up.

2.4.1 Default Download Mode

In this mode, MAD[7] is pulled down internally, GPIO[0] is the serial data
signal (SDA) and GPIO[1] is the serial clock signal (SCL). Certain data in
the serial EEPROM is automatically loaded into chip registers at power-up.

The format of the serial EEPROM data is defined in

Table 2.8

. If the

download is enabled and an EEPROM is not present or the checksum
fails, the Subsystem ID and Subsystem Vendor ID registers read back all
zeros. At power-up five bytes are loaded into the chip from locations
0xFB through 0xFF.

The Subsystem ID and Subsystem Vendor ID registers are read only in
accordance with the PCI specification, with a default value of all zeros if
the download fails.

Note:

The speed of the serial EEPROM must be 400 Kbits/s.