Avago Technologies LSI53C1010R - Manual (Page 158)

4-40 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x0B
SCSI Bus Control Lines (SBCL)
Read Only
This register returns the SCSI control line status. A bit is set when the
corresponding SCSI control line is asserted. These bits are not latched;
they are a true representation of what is on the SCSI bus at the time the
register is read. The resulting read data is synchronized before being
presented to the PCI bus to prevent parity errors from being passed to
the system. This register is only used for diagnostics testing or operation
in the low level mode.
REQ Assert SCSI REQ/ Signal 7
ACK Assert SCSI ACK/ Signal 6
BSY Assert SCSI BSY/ Signal 5
SEL Assert SCSI SEL/ Signal 4
ATN Assert SCSI ATN/ Signal 3
MSG Assert SCSI MSG/ Signal 2
C_D Assert SCSI C_D/ Signal 1
I_O Assert SCSI I_O/ Signal 0
7 6 5 4 3 2 1 0
REQ ACK BSY SEL ATN MSG C_D I_O
x x x x x x x x