Avago Technologies LSI53C1010R User Manual
Page 277
Transfer Control Instructions
5-29
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
IT[1:0]
Instruction Type –
Transfer Control Instruction
[31:30]
OPC [2:0]
Opcode
[29:27]
This 3-bit field specifies the type of transfer control
instruction to execute. All transfer control instructions can
be conditional. They can be dependent on a true/false
comparison of the ALU Carry bit, or a comparison of the
SCSI information transfer phase with the Phase field,
and/or a comparison of the First Byte Received with the
Data Compare field. Each instruction can operate in the
initiator or target mode.
Jump Instruction
The LSI53C1010R can do a true/false comparison of the
ALU carry bit, or compare the phase and/or data as
defined by the Phase Compare, Data Compare and
True/False bit fields. If the comparisons are true, it loads
the
register with the
contents of the
DMA SCRIPTS Pointer Save (DSPS)
register. The DSP register now contains the address of
the next instruction.
If the comparisons are false, the LSI53C1010R fetches
the next instruction from the address pointed to by the
register, leaving the
instruction pointer unchanged.
When the JUMP64 instruction is used, a third Dword is
fetched and loaded into the Script Fetch Selector (SFS)
register. Bit 22 indicates whether the jump is to a 32-bit
address (0) or a 64-bit address (1). All combinations of
jumps are still valid for JUMP64.
OPC2
OPC1
OPC0
Instruction Defined
0
0
0
Jump
0
0
1
Call
0
1
0
Return
0
1
1
Interrupt
1
x
x
Reserved