Avago Technologies LSI53C1010R - Manual (Page 337)

PCI and External Memory Interface Timing Diagrams 6-47
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.28 Normal/Fast Memory (
≥
128 Kbytes) Single Byte Access Write Cycle
Figure 6.28 Normal/Fast Memory (
≥
128 Kbytes) Single Byte Access Write Cycle (Cont.)
CLK
(Driven by System)
1 2 3 4 5 6 7 8 9 10
MAD
(Driven by LSI53C1010R)
High Order
Address
Middle Order
Address
Low Order
Address
MAS1/
(Driven by LSI53C1010R)
MAS0/
(Driven by LSI53C1010R)
MCE/
(Driven by LSI53C1010R)
MOE/
(Driven by LSI53C1010R)
MWE/
(Driven by LSI53C1010R)
t
13
t
11 t
12
t
24
t
25
Write
Data
Valid
t
23
t
20
CLK
(Driven by System)
11 12 13 14 15 16 17 18 19 20
MAD
(Driven by LSI53C1010R)
MAS1/
(Driven by LSI53C1010R)
MAS0/
(Driven by LSI53C1010R)
MCE/
(Driven by LSI53C1010R)
MOE/
(Driven by LSI53C1010R)
MWE/
(Driven by LSI53C1010R)
21
t
24
t
25
t
21
Valid Write Data
t
20
t
23
t
22
t
26