16 interrupt handling, Interrupt handling, Determining the synchronous transfer rate – Avago Technologies LSI53C1010R User Manual
Page 75: Figure 2.5
SCSI Functional Description
2-45
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 2.5
Determining the Synchronous Transfer Rate
2.2.16 Interrupt Handling
The SCRIPTS processors in the LSI53C1010R perform most functions
independently of the host microprocessor. However, certain interrupt
situations must be handled by the external microprocessor. This section
explains all aspects of interrupts as they apply to the LSI53C1010R.
40 MHz
Clock
Quadrupler
SCF
Divider
Asynchronous
Divider
Asynchronous
SCSI Logic
Divide by 4 (ST)
SCF2
SCF1
SCF0
SCF Divisor
0
0
0
3
0
0
1
1
0
1
0
1.5
0
1
1
2
1
0
0
3
1
0
1
4
1
1
0
6
Receive/Send
Divide by 2 (DT)
SCLK
Rate
Received Rate (DT)
Input Clock Rate
SCF Divisor
2
×
(
)
----------------------------------------------
(Megatransfers/s)
=
Receive Rate (ST)
Input Clock Rate
SCF Divisor
4
×
(
)
----------------------------------------------
(Megatransfers/s)
=
Send Rate (DT)
Input Clock Rate
SCF Divisor
2
XCLKS_DT
XCLKS_ST
XCLKH_DT
XCLKH_ST
+
+
+
2
-----------------------------------------------------------------------------------------------------------------------------------------------
+
×
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
=
Send Rate (ST)
Input Clock Rate
SCF Divisor
4
XCLKS_ST
XCLKH_ST
+
+
(
)
Ч
-------------------------------------------------------------------------------------------------------------------------
=