Avago Technologies LSI53C1010R - Manual (Page 170)

4-52 Registers
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(or INTB/) is already asserted and this bit is set, INT
remains asserted until the interrupt is serviced. At this
point the interrupt line is blocked for future interrupts until
this bit is cleared. In addition, this bit may be read and
written while SCRIPTS are executing.
Register: 0x16
Mailbox Zero (MBOX0)
Read/Write
MBOX0 Mailbox Zero [7:0]
These are general purpose bits that may be read or
written while SCRIPTS are running. They also may be
read or written by the SCRIPTS processor.
Note: The host and the SCRIPTS processor code could access
the same mailbox byte at the same time. Using one mailbox
register as read only and the other as write only prevents
this conflict.
Register: 0x17
Mailbox One (MBOX1)
Read/Write
MBOX1 Mailbox One [7:0]
These are general purpose bits that may be read or
written while SCRIPTS are running. They also may be
read or written by the SCRIPTS processor.
Note: The host and the SCRIPTS processor code could access
the same mailbox byte at the same time. Using one mailbox
register as read only and the other as write only prevents
this conflict.
7 0
MBOX0
0 0 0 0 0 0 0 0
7 0
MBOX1
0 0 0 0 0 0 0 0