Scsi control one (scntl1), Register: 0x01 – Avago Technologies LSI53C1010R User Manual
Page 146
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Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x01
SCSI Control One (SCNTL1)
Read/Write
R
Reserved
7
ADB
Assert SCSI Data Bus
6
When this bit is set, the LSI53C1010R SCSI function
drives the contents of the
register onto the SCSI data bus. When the LSI53C1010R
SCSI function is an initiator, the SCSI I/O signal must be
inactive to assert the SODL contents onto the SCSI bus.
When the LSI53C1010R SCSI function is a target, the
SCSI I/O signal must be active to assert the SODL
contents onto the SCSI bus. The contents of the SODL
register can be asserted at any time, even before the
LSI53C1010R SCSI function is connected to the SCSI
bus. Clear this bit when executing SCSI SCRIPTS. It is
normally used only for diagnostics testing or operation in
low level mode.
DHP
Disable Halt on Parity/CRC/AIP Error or ATN
(Target Only)
5
The DHP bit is only defined for the target mode. When
this bit is cleared, the LSI53C1010R SCSI function halts
the SCSI data transfer when a Parity/CRC/AIP error is
detected or when the SATN/ signal is asserted. If SATN/
or a Parity/CRC/AIP error is received in the middle of a
data transfer, the LSI53C1010R SCSI function may
transfer up to three additional bytes before halting to
synchronize between internal core cells. During
synchronous operation, the LSI53C1010R SCSI function
transfers data until there are no outstanding synchronous
offsets. If the LSI53C1010R SCSI function is receiving
data, any data residing in the DMA FIFO is sent to
memory before halting.
When this bit is set, the LSI53C1010R SCSI function
does not halt the SCSI transfer when SATN/ or a
Parity/CRC/AIP error is received.
7
6
5
4
3
2
1
0
R
ADB
DHP
CON
RST
AESP
IARB
R
0
0
0
0
0
0
0
0