Registers: 0x5c–0x5f, Registers: 0xa0–0xa3 – Avago Technologies LSI53C1010R User Manual
Page 246
4-128
Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0x5C–0x5F
Shadowed Scratch Register B (SCRATCHB)
Read/Write
SCRATCHB
Scratch Register B
[31:0]
When the PCI Configuration Info Enable bit in the
register is set,
SCRATCH Register B is placed in the shadow mode.
When read in this mode, bits [31:13] of the
register return bits
[31:13] of the PCI
Base Address Register Three (BAR3) (SCRIPTS RAM)
and bits [12:0] of SCRATCH B return zeros. Writes to the
SCRATCH B register have no effect. Resetting the PCI
Configuration Info Enable bit causes the SCRATCH B
register to return to normal operation.
Registers: 0xA0–0xA3
Shadowed Memory Move Read Selector (MMRS)
Read/Write
MMRS
Shadowed Memory Move Read Selector
[31:0]
When the PCI Configuration Info Enable bit in the
register is set, the
MMRS register is placed in the shadow mode. When read
in this mode, the
Memory Move Read Selector (MMRS)
register returns bits [31:0] of the memory mapped
operating register, PCI
Base Address Register Two (BAR2) (MEMORY)
. Writes to
the MMRS register have no effect. Clearing the PCI
Configuration Info Enable bit causes the MMRS register to
return to normal operation.
31
0
SCRATCHB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
0
MMRS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0