Avago Technologies LSI53C1010R - Manual (Page 391)

Index IX-15
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
B_SSEL+- 3-15
C_BE[7:0]/ 3-6
CLK 3-5
DEVSEL/ 3-8
ENABLE66 3-4 , 3-5
FRAME/ 3-7
GNT/ 3-8
IDSEL 3-8
INTA/ 3-4 , 3-9
INTB/ 3-4 , 3-9
IRDY/ 3-7
M66EN 3-4 , 3-5
MAD[7:0] 3-18
MAS0/ 3-18
MAS1/ 3-18
MCE/ 3-18
MOE/ 3-18
MOE/_TESTOUT 3-18
MWE/ 3-18
NC 3-21
PAR 3-6
PAR64 3-4 , 3-7
PERR/ 3-8
RBIAS 3-21
REQ/ 3-8
REQ64 3-7
RST/ 3-5
SCAN_MODE 3-19
SCLK 3-10
SERR/ 3-8
STOP/ 3-8
TCK 3-4
TCK_CHIP 3-19
TDI 3-4
TDI_CHIP 3-19
TDO_CHIP 3-19
TEST_HSC 3-4 , 3-19
TEST_RST/ 3-4 , 3-19
TMS 3-4
TMS_CHIP 3-19
TRDY/ 3-7
VDD_IO 3-20
VDDA 3-20
VDDBIAS 3-21
VDDC 3-20
VSS_IO 3-20
VSSA 3-21
VSSC 3-20
signal process (SIGP) 4-49 , 4-54
signaled system error (SSE) 4-5
simple arbitration 4-24
single
address cycles 2-21
ended SCSI signals 6-7
step interrupt (SSI) 4-42 , 4-66
step mode (SSM) 4-68
transition
data-in 2-23
data-out 2-23
transfer rates 4-111
transfer waveforms 4-106
SIP 2-50 , 2-51
SIST0 2-47
SIST1 2-47
slow memory
read cycle 6-52
write cycle 6-54
slow ROM pin 3-23
SODL
least significant byte full (OLF) 4-44
most significant byte full (OLF1) 4-46
SODL register 2-57
software reset (SRST) 4-48
source
I/O-memory enable (SIOM) 4-64
special cycle command 2-5
SREQ 2-51
stacked interrupts 2-50
start
address 5-15 , 5-24
DMA operation (STD) 4-69
sequence (START) 4-25
static block move selector (SBMS) 4-102
STOP command 2-10
stop signal 3-8
STOP/ 3-8
store instruction 2-32
stress ratings 6-2
subsystem ID 2-61 , 4-13
subsystem vendor ID 2-61 , 4-12
SURElink 1-5
SWIDE register 2-57
SYNC_IRQD (SI) 4-51
synchronous
clock conversion factor (SCF[2:0]) 4-32
data transfer rates 2-41
operation 2-41
receive rate calculation 4-104
SCSI receive 2-39
SCSI send 2-38
send rate calculation 4-105
transfer rate 2-45
system
application 1-3
error 3-8
signals 3-5