Status – Avago Technologies LSI53C1010R User Manual
Page 123
PCI Configuration Registers
4-5
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0x06–0x07
Status
Read/Write
Reads to this register behave normally. Writes are slightly different in that
bits can be cleared, but not set. A bit is cleared whenever the register is
written, and the data in the corresponding bit location is a one. For
example, to clear bit 15 and not affect any other bits, write the value
0x8000 to the register.
DPE
Detected Parity Error (from Slave)
15
This bit is set by the LSI53C1010R upon the detection of
a data parity error, even if data parity error handling
is disabled.
SSE
Signaled System Error
14
This bit is set whenever the device asserts the
SERR/ signal.
RMA
Received Master Abort (from Master)
13
A master device should set this bit when its transaction
(except for Special Cycle) is terminated with Master Abort.
RTA
Received Target Abort (from Master)
12
A master device should set this bit whenever its
transaction is terminated by Target Abort.
R
Reserved
11
DT[1:0]
DEVSEL/Timing
[10:9]
These bits encode the timing of DEVSEL/. The timings
are encoded as:
15
14
13
12
11
10
9
8
7
6
5
4
3
0
DPE SSE RMA RTA
R
DT[1:0]
DPR FBBC
R
66C NC
R
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0b00
fast
0b01
medium
0b10
slow
0b11
reserved