Avago Technologies LSI53C1010R - Manual (Page 389)

Index IX-13
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
data compare mask 5-34
data compare value 5-35
instruction type 5-29
interrupt-on-the-fly 5-33
jump address 5-35
jump if true/false 5-33
jump64 address 5-35
opcode 5-29
relative addressing 5-32
SCSI Phase 5-31
wait for valid phase 5-34
wait disconnect instruction 5-19
wait select instruction 5-17
SCSI
ACK/ 4-38 , 4-40
activity LED 2-21
asynchronous receive 2-38
asynchronous send 2-37
ATN condition - target mode (M/A) 4-70
ATN/ 4-38 , 4-40
bit mode change (SBMC) 4-77
BSY/ 4-38 , 4-40
bus control lines register (SBCL) 4-40
bus data lines (SBDL) 4-96
bus interface 2-39 , 2-41
bus mode change (SBMC) 4-73
byte count (SBC) 4-119
C_D/ 4-39 , 4-40
C_D/ signal (C_D) 4-46
chip ID (SCID) 4-33
clock 3-10
clock quadrupler 2-31
control enable (SCE) 4-88
control four (SCNTL4) 2-42
control one (SCNTL1) 2-34 , 4-28
control three (SCNTL3) 2-42 , 4-32
control two (SCNTL2) 4-30
control zero (SCNTL0) 2-34 , 4-24
cumulative byte count 4-120
destination ID register (SDID) 4-36
disconnect unexpected (SDU) 4-30
enable response to reselection 4-33
enable response to selection 4-33
enable wide SCSI 4-32
encoded destination ID 4-36 , 5-22
first byte received (SFBR) register 4-37
function A GPIO signals 3-16
function A signals 3-10
function B control 3-15
function B signals 3-13
functional description 2-18
gross error (SGE) 4-71 , 4-75
halt SCSI clock 4-89
high impedance mode (SZM) 4-88
hysteresis of receivers 6-9
I/O instructions 5-16
I_O/ 4-39 , 4-40 , 4-46
ID encoded chip 4-33
input data latch (SIDL) 4-90
input filtering 6-8
instructions
block move 5-5
I/O 5-16
read/write 5-24
interface signals 3-10
interrupt 2-51
enable one (SIEN1) 2-48 , 4-72
enable zero (SIEN0) 2-35 , 2-48 , 4-70
pending (SIP) 4-50
status one (SIST1) 2-47 , 2-48 , 2-50 , 2-52 , 4-77 , 4-
127
status zero (SIST0) 2-35 , 2-47 , 2-48 , 2-50 , 2-52 ,
4-74
latched parity 4-45
latched SCSI parity for SD[15:8] 4-47
low level mode (LOW) 4-88
LVD 2-39
mode (SMODE[1:0]) 4-91
MSG/ 4-38 , 4-40
MSG/ signal (MSG) 4-45
new phases on the SCSI bus 2-24
output control latch (SOCL) register 4-38
output data latch (SODL) 4-92
parity errors and interrupts 2-36
parity/CRC error (PAR) 4-72
parity/CRC/AIP error 4-76
performance 1-7
phase 5-13 , 5-31
phase mismatch - initiator mode 4-70
receive rate 2-43
registers 4-22
REQ/ 4-38 , 4-40
reset condition (RST) 4-72
reset SCSI offset 4-88
RST/ received (RST) 4-76
RST/ signal (RST) 4-45
SCRIPTS operation 5-1
sample instruction 5-2
SDP0/ parity signal (SDP0) 4-45
SDP1/ parity signal (SDP1) 4-47
SEL/ 4-38 , 4-40
selected as ID (SSAID[3:0]) 4-85
selection or reselection 4-77
selection or reselection time-out 4-73 , 4-77
selection time-out 4-81
selector ID register (SSID) 4-39