Avago Technologies LSI53C1010R - Manual (Page 341)

PCI and External Memory Interface Timing Diagrams 6-51
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.30 Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte Access Write Cycle (Cont.)
CLK
(Driven by System)
PAR
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1010R)
STOP/
(Driven by LSI53C1010R)
DEVSEL/
(Driven by LSI53C1010R)
AD[31:0]
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
MAD
(Driven by LSI53C1010R)
MAS1/
(Driven by LSI53C1010R)
MAS0/
(Driven by LSI53C1010R)
MCE/
(Driven by LSI53C1010R)
MOE/
(Driven by LSI53C1010R)
MWE/
(Driven by LSI53C1010R)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Byte Enable
16 32 33
Low Order
Address
Data In
Data Out
(Driven by Master)
(Driven by Master)