17 interrupt routing, Interrupt routing – Avago Technologies LSI53C1010R User Manual
Page 83
SCSI Functional Description
2-53
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.2.17 Interrupt Routing
This section documents the recommended approach to RAID ready
interrupt routing for the LSI53C1010R. To be compatible with RAID upgrade
products and the LSI53C1010R, the following requirements must be met:
•
When a RAID upgrade card is installed in the upgrade slot, interrupts
from the mainboard SCSI controller(s) assigned to the RAID upgrade
card must be routed to INTC/ and INTD/ of the upgrade slot and
isolated from the mainboard interrupt controller. The system
processor must not see interrupts from the SCSI controllers that are
serviced by the RAID upgrade card. An upgrade slot is one that is
connected to the interrupt routing logic for mainboard SCSI device(s).
When a PCI RAID upgrade board is installed into the system, it is
plugged into this slot if it is to control mainboard SCSI device(s).
•
The TDI pin of the upgrade slot must be connected to the INT_DIR/
pin of the LSI53C1010R.
•
When a RAID upgrade card is not installed, interrupts from a SCSI
core must not be presented to the system’s interrupt controller using
multiple interrupt inputs.
shows an example configuration. In this example the
LSI53C1010R contains the interrupt routing logic.
The LSI53C1010R supports four different interrupt routing modes.
Details for these modes may be found in the register description of
description in
Each
SCSI core within the chip may be configured independently by selecting
the interrupt routing mode using bits [1:0] in the STEST1 register within
each core. Mode 0 is the default mode and is compatible with RAID
upgrade products.
If the implementation shown in
is used, INTC/ and INTD/ of
the PCI RAID upgrade slot cannot be used when a non-RAID upgrade
card is installed in the slot. If this restriction is not acceptable, additional
buffer logic must be implemented on the mainboard. As long as these
interrupt routing requirements are satisfied, a mainboard designer could
implement this design with external logic.