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Avago Technologies LSI53C1010R User Manual

Page 390

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IX-14

Index

Version 2.2

Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.

send rate

2-44

shadow registers

4-125

single-ended

2-39

SODL register

2-57

status one (SSTAT1)

2-35

,

4-45

status two (SSTAT2)

2-35

,

4-46

status zero (SSTAT0)

2-35

,

4-44

synchronous offset maximum (SOM)

4-86

synchronous offset zero (SOZ)

4-85

synchronous operation

2-41

synchronous receive

2-39

synchronous send

2-38

termination

2-39

test four (STEST4)

4-91

test one (STEST1)

4-86

test three (STEST3)

4-89

test two (STEST2)

4-88

test zero (STEST0)

4-85

timer one (STIME1)

4-82

timer zero (STIME0)

4-80

timing diagrams

6-58

TolerANT technology

1-6

transfer (SXFER)

4-34

Ultra160 SCSI

2-22

Ultra160 transfer enable

4-103

unexpected disconnect

4-72

,

4-76

valid (VAL)

4-39

wide residue (SWIDE)

4-78

wide SCSI receive

4-31

wide SCSI receive bit

2-56

wide SCSI send

4-31

wide SCSI send bit

2-56

SCSI-1

transfers (single-ended 5.0 Mbytes)

6-60

SCSI-2

fast transfers

6-61

,

6-63

second dword

5-15

,

5-24

,

5-26

,

5-35

,

5-38

,

5-42

select

2-19

during selection

2-41

instruction

5-18

with ATN/

5-22

with SATN/ on a start sequence (WATN)

4-26

selected (SEL)

4-71

,

4-75

selection

4-33

selection or reselection time-out (STO)

4-73

,

4-77

selection response logic test (SLT)

4-85

selection time-out

4-81

semaphore (SEM)

4-49

send rate calculation

2-44

serial EEPROM

data format

2-61

interface

2-60

SERR/

3-8

SERR/enable (SE)

4-3

set instruction

5-17

SCRIPTS

5-19

set/clear

carry

5-22

SACK/

5-23

SATN/

5-23

target mode

5-22

SIDL

least significant byte full (ILF)

4-44

most significant byte full (ILF1)

4-46

SIEN0

2-48

SIEN1

2-48

signal

grouping

3-3

types

3-2

signal descriptions

A_DIFFSENS

3-11

A_GPIO0

3-16

A_GPIO1

3-16

A_GPIO2

3-16

A_GPIO3

3-16

A_GPIO4

3-16

A_SACK+-

3-12

A_SATN+-

3-12

A_SBSY+-

3-12

A_SCD+-

3-12

A_SDP[1:0]+-

3-11

A_SIO+-

3-12

A_SMSG+-

3-12

A_SREQ+-

3-12

A_SRST+-

3-12

A_SSEL+-

3-12

ACK64/

3-7

AD[63:0]

3-6

ALT_INTA/

3-4

,

3-9

ALT_INTB/

3-4

,

3-9

B_DIFFSENS

3-14

B_GPIO

3-17

B_GPIO1

3-17

B_GPIO2

3-17

B_GPIO3

3-17

B_GPIO4

3-17

B_SACK+-

3-15

B_SATN+-

3-15

B_SBSY+-

3-15

B_SCD+-

3-15

B_SD[15:0]+-

3-13

B_SDP[1:0]+-

3-13

B_SIO+-

3-15

B_SMSG+-

3-15

B_SREQ+-

3-15

B_SRST+-

3-15