Avago Technologies LSI53C1010R User Manual
Page 390

IX-14
Index
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
send rate
shadow registers
single-ended
SODL register
status one (SSTAT1)
status two (SSTAT2)
status zero (SSTAT0)
synchronous offset maximum (SOM)
synchronous offset zero (SOZ)
synchronous operation
synchronous receive
synchronous send
termination
test four (STEST4)
test one (STEST1)
test three (STEST3)
test two (STEST2)
test zero (STEST0)
timer one (STIME1)
timer zero (STIME0)
timing diagrams
TolerANT technology
transfer (SXFER)
Ultra160 SCSI
Ultra160 transfer enable
unexpected disconnect
,
valid (VAL)
wide residue (SWIDE)
wide SCSI receive
wide SCSI receive bit
wide SCSI send
wide SCSI send bit
SCSI-1
transfers (single-ended 5.0 Mbytes)
SCSI-2
fast transfers
,
second dword
,
,
,
select
during selection
instruction
with ATN/
with SATN/ on a start sequence (WATN)
selected (SEL)
selection
selection or reselection time-out (STO)
,
selection response logic test (SLT)
selection time-out
semaphore (SEM)
send rate calculation
serial EEPROM
data format
interface
SERR/
SERR/enable (SE)
set instruction
SCRIPTS
set/clear
carry
SACK/
SATN/
target mode
SIDL
least significant byte full (ILF)
most significant byte full (ILF1)
SIEN0
SIEN1
signal
grouping
types
signal descriptions
A_DIFFSENS
A_GPIO0
A_GPIO1
A_GPIO2
A_GPIO3
A_GPIO4
A_SACK+-
A_SATN+-
A_SBSY+-
A_SCD+-
A_SDP[1:0]+-
A_SIO+-
A_SMSG+-
A_SREQ+-
A_SRST+-
A_SSEL+-
ACK64/
AD[63:0]
ALT_INTA/
,
ALT_INTB/
,
B_DIFFSENS
B_GPIO
B_GPIO1
B_GPIO2
B_GPIO3
B_GPIO4
B_SACK+-
B_SATN+-
B_SBSY+-
B_SCD+-
B_SD[15:0]+-
B_SDP[1:0]+-
B_SIO+-
B_SMSG+-
B_SREQ+-
B_SRST+-