Avago Technologies LSI53C1010R - Manual (Page 8)

viii Contents
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.2.7 Opcode Fetch Burst Capability 2-32
2.2.8 Load and Store Instructions 2-33
2.2.9 JTAG Boundary Scan Testing 2-33
2.2.10 Parity/CRC/AIP Options 2-34
2.2.11 DMA FIFO 2-36
2.2.12 SCSI Data Paths 2-37
2.2.13 SCSI Bus Interface 2-39
2.2.14 Select/Reselect during Selection/Reselection 2-41
2.2.15 Synchronous Operation 2-41
2.2.16 Interrupt Handling 2-45
2.2.17 Interrupt Routing 2-53
2.2.18 Chained Block Moves 2-55
2.3 Parallel ROM Interface 2-59
2.4 Serial EEPROM Interface 2-60
2.4.1 Default Download Mode 2-60
2.4.2 No Download Mode 2-61
2.5 Power Management 2-61
2.5.1 Power State D0 2-62
2.5.2 Power State D1 2-62
2.5.3 Power State D2 2-63
2.5.4 Power State D3 2-63
Chapter 3 Signal Descriptions
3.1 Signal Organization 3-1
3.2 Internal Pull-ups and Pull-downs on LSI53C1010R Signals 3-4
3.3 PCI Bus Interface Signals 3-5
3.3.1 System Signals 3-5
3.3.2 Address and Data Signals 3-6
3.3.3 Interface Control Signals 3-7
3.3.4 Arbitration Signals 3-8
3.3.5 Error Reporting Signals 3-8
3.3.6 Interrupt Signals 3-9
3.4 SCSI Bus Interface Signals 3-10
3.4.1 SCSI Function A Signals 3-10
3.4.2 SCSI Function B Signals 3-13
3.5 General Purpose I/O (GPIO) Signals 3-16
3.6 Flash ROM and Memory Interface Signals 3-18