Avago Technologies LSI53C1010R - Manual (Page 12)

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Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
6.6 Input Current as a Function of Input Voltage 6-9
6.7 Output Current as a Function of Output Voltage 6-10
6.8 External Clock 6-11
6.9 Reset Input 6-12
6.10 Interrupt Output 6-12
6.11 PCI Configuration Register Read 6-15
6.12 PCI Configuration Register Write 6-16
6.13 Operating Registers/SCRIPTS RAM Read, 32 Bits 6-17
6.14 Operating Register/SCRIPTS RAM Read, 64 Bits 6-18
6.15 Operating Register/SCRIPTS RAM Write, 32 Bits 6-19
6.16 Operating Register/SCRIPTS RAM Write, 64 Bits 6-20
6.17 Nonburst Opcode Fetch, 32-Bit Address and Data 6-22
6.18 Burst Opcode Fetch, 32-Bit Address and Data 6-24
6.19 Back to Back Read, 32-Bit Address and Data 6-26
6.20 Back to Back Write, 32-Bit Address and Data 6-28
6.21 Burst Read, 32-Bit Address and Data 6-30
6.22 Burst Read, 64-Bit Address and Data 6-32
6.23 Burst Write, 32-Bit Address and Data 6-34
6.24 Burst Write, 64-Bit Address and Data 6-36
6.25 External Memory Read 6-38
6.26 External Memory Write 6-42
6.27 Normal/Fast Memory (
≥
128 Kbytes) Single Byte
Access Read Cycle 6-45
6.28 Normal/Fast Memory (
≥
128 Kbytes) Single Byte
Access Write Cycle 6-47
6.29 Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte
Access Read Cycle 6-48
6.30 Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte
Access Write Cycle 6-50
6.31 Slow Memory (
≥
128 Kbytes) Read Cycle 6-53
6.32 Slow Memory (
≥
128 Kbytes) Write Cycle 6-55
6.33
≤
64 Kbytes ROM Read Cycle 6-56
6.34
≤
64 Kbytes ROM Write Cycle 6-57
6.35 Initiator Asynchronous Send 6-58
6.36 Initiator Asynchronous Receive 6-59
6.37 Target Asynchronous Send 6-59
6.38 Target Asynchronous Receive 6-60
6.39 Initiator and Target ST Synchronous Transfer 6-62