Avago Technologies LSI53C1010R - Manual (Page 238)

4-120 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
determine the correct address to start fetching data from
after a phase mismatch, this byte is not counted for this
BMOV. It is included in the previous BMOV’s byte count.
Register: 0xDB
Reserved
This register is reserved.
Registers: 0xDC–0xDF
Cumulative SCSI Byte Count (CSBC)
Read/Write
CSBC Cumulative SCSI Byte Count [31:0]
This loadable register contains a cumulative count of the
number of bytes transferred across the SCSI bus during
data phases. It does not count bytes sent in command,
status, Message-In or Message-Out phases. It counts
bytes as long as the phase mismatch enable bit (ENPMJ)
in the
Chip Control Zero (CCNTL0) register is set. Unlike
the SCSI Byte Count (SBC) , this count is not cleared on
each BMOV instruction but continues to count across
multiple BMOV instructions. This register can be loaded
with any arbitrary start value.
7 0
R
x x x x x x x x
31 0
CSBC
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0