Avago Technologies LSI53C1010R User Manual
Page 74
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Functional Description
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
The synchronous send rate, in units of megatransfers/s, can be
calculated using the following formula:
To configure the LSI53C1010R for Ultra160 DT transfers, perform the
following steps:
1.
Enable the SCSI Clock Quadrupler – The LSI53C1010R can
quadruple the frequency of a 40 MHz SCSI clock, allowing the
system to perform Ultra160 SCSI transfers. This option is user
selectable through bit settings in the
register. At power-up or reset, the quadrupler is disabled and
powered down. Follow the steps in the bit description to enable the
clock quadrupler.
2.
Program the Transfer Rate – Using SCNTL3 and SCNTL4, program
the register to the 160 Mbytes/s transfer rate.
3.
Program the Maximum SCSI Offset – Using SXFER, program the
maximum SCSI DT Synchronous offset to 0x3E.
4.
Enable TolerANT – Set the TolerANT Enable bit,
, bit 7. Active negation must be enabled
for the LSI53C1010R to perform Ultra160 SCSI transfers.
illustrates the clock division factors used in each register as
well as the role of the register bits in determining the transfer rate. An
example of configuring the Ultra160 SCSI transfer speed is:
1.
Set SCNTL3 to 0x18.
2.
Set SXFER to 0x3E.
3.
Set SCNTL4 to 0x80.
These settings program the LSI53C1010R SCSI clocks to send and
receive at 160 MHz with a synchronous SCSI offset of 0x3E.
Send Rate (DT)
Input Clock Rate
SCF Divisor
2
XCLKS_DT + XCLKS_ST + XCLKH_DT + XCLKH_ST
2
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+
×
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=
Send Rate (ST)
Input Clock Rate
SCF Divisor
4
XCLKS_ST + XCLKH_ST
+
(
)
Ч
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=