Avago Technologies LSI53C1010R User Manual

Page 60

2-30

Functional Description

Version 2.2

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Bit 6, DCRCPC (Disable CRC Protocol Checking) causes the
LSI53C1010R to not check for a CRC request prior to a phase
change on the SCSI bus. This condition creates a SCSI error
condition and makes the device noncompliant with the SPI-3
specification. Do not set this bit under normal operating conditions.

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Bits [5:0] are reserved.

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The

CRC Control One (CRCCNTL1)

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Bit 7, CRCERR (CRC Error), indicates whether or not a CRC
error has been detected during a DT Data In SCSI transfer. This
bit is independent of the DCRCC bit setting. To clear this
condition, either write this bit to a one or read the SIST0 and
SIST1 registers. When CRC checking and the Parity/CRC/AIP
Error interrupt are both enabled, CRCERR is mirrored in the
SIST0 register, bit 0, as a Parity/CRC/AIP error.

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Bit 6 is reserved.

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Bit 5, ENAS (Enable CRC Auto Seed), is set to cause the CRC
logic to reseed itself automatically after every CRC check
performed during DT Data In SCSI transfers. When this bit is
cleared, the SCSI control logic controls when the CRC logic is
reseeded.

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Bit 4, TSTSD (Test CRC Seed), is set to cause the CRC logic to
reseed itself immediately. Do not set this bit during normal
operation because it may cause corrupt CRCs to be generated.

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Bit 3, TSTCHK (Test CRC Check), is set to cause the CRC logic
to initiate a CRC check. Do not set this bit during normal
operation because it creates spurious CRC errors.

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Bit 2, TSTADD (Test CRC Accumulate), is set to cause the CRC
block to include the value present in the input register in the current
CRC calculation. A new output CRC value results. Do not set this
bit during normal operation because corrupt CRC values result.

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Bits [1:0], CRCDSEL[1:0] (CRC Data Register Selector), control
the data visible in the CRC Data register.

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The

CRC Data (CRCD)

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Bits [31:0] CRCDATA (CRC Data). The value in this register is
dependent upon the setting of the CRCDSEL bits.