Phase mismatch jump address one (pmjad1), Phase mismatch jump address two (pmjad2), Registers: 0xc0–0xc3 – Avago Technologies LSI53C1010R User Manual
Page 233: Registers: 0xc4–0xc7
SCSI Registers
4-115
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0xC0–0xC3
Phase Mismatch Jump Address One (PMJAD1)
Read/Write
PMJAD1
Phase Mismatch Jump Address One
[31:0]
This register contains the 32-bit address that is jumped
to upon a phase mismatch. Depending upon the state of
the PMJCTL bit, this address is either used during an
outbound (Data-Out, Command, Message-Out) phase
mismatch (PMJCTL = 0) or when the WSR bit is cleared
(PMJCTL = 1). This register is loaded with the address of
a SCRIPTS routine that updates the memory data
structures of the BMOV that was executing when the
phase mismatch occurred.
Registers: 0xC4–0xC7
Phase Mismatch Jump Address Two (PMJAD2)
Read/Write
PMJAD2
Phase Mismatch Jump Address Two
[31:0]
This register contains the 32-bit address that is jumped
to upon a phase mismatch. Depending upon the state of
the PMJCTL bit, this address is either used during an
inbound (Data-In, Status, Message-In) phase mismatch
(PMJCTL = 0) or when the WSR bit is set (PMJCTL = 1).
This register is loaded with the address of a
SCRIPTS routine that updates the memory data
structures of the BMOV that was executing when the
phase mismatch occurred.
31
0
PMJAD1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
0
PMJAD2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0